In the rapidly advancing semiconductor manufacturing industry, complementary metal oxide semiconductor (CMOS) FinFET devices may be used in many logic circuits and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins having high aspect ratios in which the channel and source/drain regions for the transistor are formed. A gate is formed over and along the sides of a portion of the semiconductor fins. The increased surface area of the channel and source/drain regions in a FinFET as compared to a planar transistor having the same area results in faster, more reliable and better-controlled semiconductor transistor devices.
Different FinFETs having different fin pitches are used in different areas of a semiconductor apparatus. The differences in fin pitch results in different areas having different fin densities. During fin formation, a localized etch loading effect causes areas having different fin densities to have different fin heights. Depending on the etch process, low fin density areas may have longer fins or shorter fins relative to high fin density areas.
Process-induced fin height variations affect the electrical properties of the FinFETs. While chemical and process tuning can improve the fin height uniformity, better fin height control in different fin density areas continues to be sought.